UM0434 datasheet(265/390 Pages) STMICROELECTRONICS

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External core complex interfaces

UM0434

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Read transfers consist of the following:

●

A request cycle, where address and attributes are driven along with a transfer request

●

One or more memory access cycles to perform accesses and return data to the CPU

for alignment, sign or zero extension, and forwarding.

Write transfers consist of a request cycle, in which address and attributes are driven along

with a transfer request; and of one or more data drive cycles, in which write data is driven

and external devices accept write data for the access.

To support sustained single-cycle transfers, access requests can overlap. Up to two access

requests may be in progress during any cycle—one access outstanding and a second in the

pending request phase. If access retraction is enabled via HID1[ARD] = 0, the BIU is free to

change the current request at any time, even if part of a burst transfer.

Access requests are assumed to be accepted as long as either no access is in progress or

an access is terminated during the same cycle when a new request is active (

p_[d,i]_hready

asserted). When an access is accepted, the BIU is free to change the current request.

The local memory control logic is responsible for proper pipelining and latching of all

interface signals to initiate memory accesses.

The system hardware can use

p_hresp[2:0] to signal, using the ERROR response encoding,

that the current bus cycle has an error when a fault is detected. ERROR assertion requires a

2-cycle response. In the first cycle of the response,

p_hresp[2:0] are driven to indicate

ERROR and

p_[d,i]_hready must be negated. During the following cycle, the ERROR

response must continue to be driven, and

p_[d,i]_hready must be asserted. When the core

recognizes a bus error condition for an access at the end of the first cycle of the 2-cycle

error response, a subsequent pending access request may be removed by the BIU driving

p_[d,i]_htrans[2:0] to the IDLE state in the second cycle of the 2-cycle error response. Not

all pending requests are removed, however.

When a bus cycle is terminated with a bus error, the core can enter storage error exception

processing immediately following the bus cycle, or it can defer processing the exception.

The instruction prefetch mechanism requests instruction words from the instruction memory

unit before it is ready to execute them. If a bus error occurs on an instruction fetch, the core

does not take the exception until it attempts to use the instruction. Should an intervening

instruction cause a branch, or should a task switch occur, the storage error exception for the

unused access does not occur. A bus error termination for any write access or read access

that references data specifically requested by the execution unit causes the core to begin

exception processing.

Basic read transfer cycles

During a read transfer, the core receives data from a memory or peripheral device.

Figure 33 shows functional timing for basic read transfers, and clock-by-clock descriptions of

activity follow.

UM0434 Datasheet(PDF) 265 Page - STMicroelectronics

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