UM0434 datasheet(262/390 Pages) STMICROELECTRONICS

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UM0434

External core complex interfaces

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Figure 32 shows an example for designing an external JTAG register set using the inputs

and outputs provided along with the JTAG primary inputs. The main components are a clock

generation unit, a JTAG shifter (load, shift, hold, clr), the registers (load, hold, clr), and an

input mux to the shifter for the serial output back to the core.The shifter and the registers

may be as wide as the application warrants [0:x]. The length determines the number of

states the TAP controller is held in Shift_DR (x+1).

Figure 32.

Example external JTAG register design

9.3.2

JTAG ID signals

Table 187 shows the JTAG ID register unique to Freescale as specified by the IEEE 1149.1

JTAG Specification. Note that bit 31 is the msb of this register.

j_serial_data

Serial data. Receives serial data from external JTAG registers. All external registers share

this serial output back to the core. Therefore it must be muxed using

j_gp_regsel[0:11],

j_lsrl_regsel, and j_en_once_regsel. The data is internally routed to j_tdo.

j_key_in

Key data in. Receives serial data from logic to indicate a key or other value to be scanned

out in the Shift_IR state when the current value in the IR is the Enable_OnCE instruction.

This input is provided to assist in implementing security logic outside of the core, which

conditionally asserts

jd_en_once. During the Shift_IR state, when jd_en_once is negated,

this input is sampled on the rising edge of

j_tclk, and, after a 2-clock delay, the data is

internally routed to

j_tdo. This allows provision of a key value via the j_tdo output following

a transition from Capture_IR to Shift_IR.

j_key_in provides the key value.

Table 186.

Descriptions of JTAG interface signals (continued)

Signal

I/O

Signal description

Shifter

Data

REG0

REG1

j_gp_regsel[1:0]

reg0_dat

reg1_dat

clk_reg0 2

clk_reg13

clk_reg0 = j_tclk & j_update_gp_reg & j_gp_regsel[0]

clk_reg1 = j_tclk & j_update_gp_reg & j_gp_regsel[1]

j_serial_data

j_tdi

clk_shfter 1

clk_shfter = j_tclk & (j_shift_dr | j_capture_dr)

CLK

GEN

j_tclk

j_gp_regsel[1:0]

j_shift_dr

j_update_gp_reg

SHIFT

LOAD

j_capture_dr

j_shift_dr

j_capture_dr

j_trst_b

NOTES:

UM0434 Datasheet(PDF) 262 Page - STMicroelectronics

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