UM0434 datasheet(259/390 Pages) STMICROELECTRONICS

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External core complex interfaces

UM0434

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Table 184 lists interface signals that assist in implementing a real-time development tool

capability with a controller that is external to the core. These signals are described in

Chapter 12.11: Nexus3 pin interface on page 371.”

Table 185 lists the primary JTAG interface signals. These signals are usually connected

directly to device pins (except for

j_tdo, which needs tri-state and edge support logic),

unless JTAG TAP controllers are concatenated.

Table 186 describes JTAG interface signals.

Table 184.

core development support (Nexus3) signals

Signal

Type

Description

nex_mcko

Nexus3 clock output

nex_rdy_b

Nexus3 ready output

nex_evto_b

Nexus3 event-out output

nex_evti_b

Nexus3 event-in input

nex_mdo[n:0]

Nexus3 message data output

nex_mseo_b[1:0]

Nexus3 message start/end output

Table 185.

JTAG primary interface signals

Signal name

Type

Description

j_trst_b

JTAG test reset

j_tclk

JTAG test clock

j_tms

JTAG test mode select

j_tdi

JTAG test data input

j_tdo

Test data out to master controller or pad

j_tdo_en

Enables TDO output buffer.

j_tdo_en is asserted when the TAP controller

is in the shift_dr or shift_ir state.

Table 186.

Descriptions of JTAG interface signals

Signal

I/O

Signal description

j_tdi

JTAG/OnCE serial input. Provides data and commands to the OnCE controller. Data is

latched on the rising edge of

j_tclk. Data is shifted into the OnCE serial port lsb first.

j_tclk

JTAG/OnCE serial clock. Supplies the serial clock to the OnCE control block. The serial

clock provides pulses required to shift data and commands into and out of the OnCE serial

port (data is clocked into the OnCE on the rising edge and is clocked out of the OnCE

serial port on the rising edge). The debug serial clock frequency must not exceed 50% of

the processor clock frequency.

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