UM0434 datasheet(273/390 Pages) STMICROELECTRONICS

273 / 390 page

External core complex interfaces

UM0434

274/391

Figure 40 shows another sequence of read and write cycles. In this example, reads incur a

single wait state.

Figure 40.

Multi-Cycle read with Wait-State, Single-Cycle write,

read with Wait-State, Single-Cycle write, full pipelining -

The first read request (addrx) is taken at the end of cycle C1 because the bus is idle.

The first write request (addry) is not taken at the end of cycle C2 because no ready

response is signaled and only one access can be outstanding (addrx). It is taken at the end

of C3 once the first read request has signaled a ready/OKAY response.

Data for the addry write cycle is driven in C4, the cycle after the access is taken. The second

read request (addrz) is taken during C4 because the addry write is terminating.

A second write request (addrw) is not taken at the end of C5 because the second read

access is not terminating, and it continues to drive the address and attributes into cycle C6.

During C6, the addrz read access is terminated and the addrw write access is taken.

In cycle C7, data for the addrw write access is driven. During C7, a ready/OKAY response is

asserted to complete the write cycle to addrw. No further accesses are requested, so

p_[d,i]_htrans signals IDLE.

nonseq

idle

addr x

addr y

addr z

addr w

single

data x

data z

data y

data w

okay

123

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

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