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UM0434 Datasheet(PDF) 276 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 276 Page - STMicroelectronics |
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276 / 390 page  UM0434 External core complex interfaces 277/391 An example of a misaligned write cycle followed by an aligned read cycle is shown in Figure 43. It is similar to the example in Figure 42. Figure 43. Misaligned write, single cycle read transfer, full pipelining 9.5.2 Burst accesses Figure 44 shows functional timing for a burst read transfer. Figure 44. Burst read transfer nonseq nonseq nonseq idle addr x addr x+ addr y single single single ** data y data x data x+ okay okay okay okay 1 234 5 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp nonseq seq seq seq ... addr x addr x+8 addr x+16 addr x+24 INCR data x data x+8 data x+16 data x+24 okay okay okay okay okay Burst Read 12 3 4 5 6 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp |
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