UM0434 datasheet(280/390 Pages) STMICROELECTRONICS

280 / 390 page

UM0434

External core complex interfaces

281/391

Figure 49 shows functional timing for a burst read with wait-state transfer where the second

beat to addr x+8 is retracted and replaced with a new burst transfer.

Figure 49.

Burst read with Wait-State transfer, retraction

The 1st cycle of the burst incurs a single wait state, & the burst is replaced by another burst.

Figure 50 shows functional timing for a burst write transfer. The 2nd burst is only 1 beat long.

Figure 50.

Burst write transfers, Single-Beat burst

This same scenario can occur for read bursts as well.

nonseq

seq

idle

addr x

addr y+8

addr y+16

incr

data x

data y

data y+8

data y+16

okay

Burst Read with wait-state

23456

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

addr y

addr x+8

nonseq

seq

nonseq

idle

addr x

addr x+8

addr x+16

addr y

incr

data x

data x+8

data x+16

data y

okay

Burst Write

1234

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

UM0434 Datasheet(PDF) 280 Page - STMicroelectronics

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