UM0434 datasheet(282/390 Pages) STMICROELECTRONICS

282 / 390 page

UM0434

External core complex interfaces

283/391

Figure 52.

Burst read with Wait-State transfer, retraction

The first cycle of the burst incurs a single wait-state, and the burst is replaced by another

burst. Replacement by a single access is also possible.

Address retraction does not occur on a requested write cycle, only on read cycles. It also

may occur any time during a burst cycle.

Error termination operation

The

p_[d,i]_hresp[2:0] inputs signal an error termination for an access in progress. The

ERROR encoding is used with the assertion of

p_[d,i]_hready to terminate a cycle with

error. Error termination is a two-cycle termination; the first cycle consists of signaling the

ERROR response on

p_[d,i]_hresp[2:0] while holding p_[d,i]_hready negated, and during

the second cycle, asserting

p_[d,i]_hready while continuing to drive the ERROR response

p_[d,i]_hresp[2:0]. This 2-cycle termination allows the BIU to retract a pending access if it

desires to do so.

p_[d,i]_htrans may be driven to IDLE during the second cycle of the two-

cycle error response, or may change to any other value, and a new access unrelated to the

pending access may be requested. The cycle that may have been previously pending while

waiting for a response that terminates with error may be changed. It is not required to

remain unchanged when an error response is received.

nonseq

seq

idle

addr x

addr y+8

addr y+16

incr

data x

data y

data y+8

data y+16

okay

Burst Read with wait-state

12345

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

addr y

addr x+8

nonseq

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