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UM0434 Datasheet(PDF) 286 Page - STMicroelectronics

Part # UM0434
Description  The primary objective of this user?셲 manual is to describe
PDF  390 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM0434 Datasheet(HTML) 286 Page - STMicroelectronics

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UM0434
External core complex interfaces
287/391
Figure 56 shows another example of error termination, this time on the initial portion of a
burst read. The aborted burst is followed by a burst write.
Figure 56.
Burst read with error termination, burst write
The first portion of the burst read request is terminated with error. The second portion is
aborted by the CPU during the second cycle of the two cycle error response, and a
subsequent burst write access to addry becomes pending instead.
9.5.4
Address retraction
Address retraction is the process of replacing a request with a new unrelated one. Although
the AMBA AHB protocol requires an access request to remain driven unchanged once
presented on the bus, higher system performance may be obtained if this aspect of the
protocol is modified to allow an access request to be changed before being taken.
Figure 57 shows an example of address retraction during wait state operation. Signal
p_hready for the first request (addr
x) is not asserted during C2, so a wait state is inserted
during C3 until
p_hready is recognized.
Meanwhile, a subsequent request has been generated by the CPU for addry which is not
taken in C2 since the previous transaction is still outstanding. The address and transfer
attributes are retracted in cycle C3, and a new access to addrz is requested and made at the
end of C3 because the previous access is completing. Data for addrx and a ready/OKAY
response are driven back by the slave device. In cycle C4, a request for addrw is made. The
request for access to addrw is taken at the end of C4; during C5, the data and a ready/OKAY
response are provided by the slave device. In cycle C5, no further accesses are requested.
nonseq
seq
idle
nonseq
seq
seq
seq
idle
addr x
addr x+8
addr y
addr y+8
addr y+16
addr y+24
wrap4
wrap4
data x
data y
y+8
y+16
y+24
okay
error
error
okay
okay
okay
okay
okay
12
34
567
8
m_clk
p_htrans
p_addr,p_hprot
p_hsize,
p_hbstrb, etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp



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