UM0434 datasheet(284/390 Pages) STMICROELECTRONICS

284 / 390 page

UM0434

External core complex interfaces

285/391

Figure 54.

Data read with error, data write retracted, instruction read, full pipelining

The first read request (addrx) is taken at the end of cycle C1 because the bus is idle. It is a

data read.

The second request (write to addry) is not taken at the end of C2 because the first access is

still outstanding (no

p_[d,i]_hready assertion). An error response is signaled by the

addressed slave for addrx by driving ERROR onto the p_[d,i]_hresp[2:0] inputs. This is the

first cycle of the two cycle error response protocol.

p_[d,i]_hready is asserted during C3 for the first read access (addr

x) while the ERROR

encoding remains driven on

p_[d,i]_hresp[2:0], terminating the access. The read data bus is

undefined.

In this example of error termination, the CPU retracts the requested access to addry by

driving

p_[d,i]_htrans signals to the IDLE state during the second cycle of the two-cycle

error response.

A different access to addrz is requested during C4 and is taken at the end of C4. During C5,

read data is supplied for the addrz read, and the access is terminated normally.

In this example of error termination, a subsequent access was aborted.

nonseq

idle

nonseq

idle

addr x

addr y

addr z

single

data x

data z

okay

error

okay

m_clk

p_htrans

p_addr,p_hprot

p_hsize,

p_hbstrb, etc

p_hburst

p_hunalign

p_hwrite

p_hrdata

p_hwdata

p_hready

p_hresp

UM0434 Datasheet(PDF) 284 Page - STMicroelectronics

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