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UM0434 Datasheet(PDF) 279 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 279 Page - STMicroelectronics |
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279 / 390 page  External core complex interfaces UM0434 280/391 The first cycle of the burst incurs a single wait-state. Data for the second beat of the burst is valid the cycle after the second beat is taken. Figure 48 shows functional timing for a pair of burst read transfers. Figure 48. Burst read transfers Note that in this example the first burst is two beats long and is followed immediately by a second burst which is unrelated to the first. Note: Bursts may be of any length (including a single beat) and may be followed immediately by any type of transfer. No idle cycles are required. nonseq seq nonseq seq ... addr x addr x+8 addr y addr y+8 incr data x data x+8 data y data y+8 okay okay okay okay okay Burst Read 12 3 4 5 6 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp |
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