UM0434 datasheet(321/390 Pages) STMICROELECTRONICS

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Debug support

UM0434

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Emulation firmware should modify the CTL, PC, and IR values in the CPUSCR during

execution of debug-related instructions as well as just before exiting debug with a Go+Exit

FFRA

Feed forward RA operand bit. This control bit causes the content of the WBBRlower to be used as

the rA (rS for logical and shift operations) operand value of the first instruction to be executed

following an update of the CPUSCR. This allows the debug firmware to update processor

registers, initialize the WBBRlower with the desired value, set the FFRA bit, and execute an ori

Rx,Rx,0 instruction to the desired register.

0 No action

1 Content of WBBR used as rA (rS for logical and shift operations) operand value

IRSTAT0

IR status bit 0.This control bit indicates an ERROR termination status for the IR.

0 No TEA occurred on the fetch of this instruction.

1 A TEA occurred on the fetch of this instruction

IRSTAT1

IR status bit 1. Indicates a TLB miss status for the IR.

0 No TLB miss occurred on the fetch of this instruction.

1 TLB miss occurred on the fetch of this instruction.

IRSTAT2

IR status bit 2. Indicates an instruction address compare 1 event status for the IR.

0 No instruction address compare 1 event occurred on the fetch of this instruction.

1 An instruction address compare 1 event occurred on the fetch of this instruction.

IRSTAT3

IR status bit 3. Indicates an instruction address compare 2 event status for the IR.

0 No instruction address compare 2 event occurred on the fetch of this instruction.

1 An instruction address compare 2 event occurred on the fetch of this instruction.

IRSTAT4

IR status bit 4. Indicates an instruction address compare 3 event status for the IR.

0 No instruction address compare 3 event occurred on the fetch of this instruction.

1 An instruction address compare 3 event occurred on the fetch of this instruction.

IRSTAT5

IR status bit 5. Indicates an instruction address compare 4 event status for the IR.

0 No instruction address compare 4 event occurred on the fetch of this instruction.

1 An instruction address compare 4 event occurred on the fetch of this instruction.

IRSTAT6

IR status bit 6. This control bit indicates a parity error status for the IR.

0 No parity error occurred on the fetch of this instruction.

1 A parity error occurred on the fetch of this instruction.

IRSTAT7

IR status bit 7. Indicates a precise external termination error status for the IR.

0 No precise external termination error occurred on the fetch of this instruction.

1 Precise external termination error occurred on the fetch of this instruction.

IRSTAT8

IR status bit 8. Indicates the VLE status for the IR. IRStat8 affects the behavior of IRStat9.

0 IR contains a BookE instruction.

1 IR contains a VLE instruction, aligned in the most significant portion of IR if 16-bit.

IRSTAT9

IR status bit 9. Indicates the VLE byte-ordering error status for the IR or a Book E misaligned

instruction fetch, depending on the state of IRStat8.

0 IR contains an instruction without a byte-ordering error and no misaligned instruction fetch

exception has occurred (no MIF).

1 If IRStat8 = 0, A Book E misaligned instruction fetch exception occurred while filling the IR.

If IRStat8 = 1, IR contains an instruction with a byte-ordering error due to mismatched VLE

page attributes, or due to E indicating little-endian for a VLE page.

Table 208.

CTL field definitions (continued)

Bits

Name

Description

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