UM0434 datasheet(324/390 Pages) STMICROELECTRONICS

324 / 390 page

UM0434

Debug support

325/391

Figure 71.

OnCE PC FIFO

The FIFO is not affected by the operations performed during a debug session except for the

FIFO pointer increment when reading the FIFO. When entering debug mode, the FIFO

counter is pointing to the FIFO register containing the address of the oldest of the eight

change-of-flow prefetches. When OCMD [RS] is loaded with the value corresponding to the

PC FIFO (010 1101), the current pointer value is captured into a temporary register. This

temporary value (not the actual FIFO counter) is incremented as FIFO reads are performed.

The first FIFO read obtains the oldest address and the following FIFO read returns the other

addresses from the oldest to the newest (the order of execution).

Updates to the FIFO are frozen whenever the OCMD register contains a command whose

RS[0–6] field points to the PC FIFO (010 1101) to allow firmware to read the contents of the

PC FIFO without placing the CPU into debug mode. After completing all accesses to the PC

PC FIFO Register 0

TDO

TCK

PC FIFO Register 1

PC FIFO Register 2

PC FIFO Register 3

PC FIFO Register 4

Instruction Fetch Address

Circular

Buffer

Pointer

PC FIFO Shift Register

PC FIFO Register 5

PC FIFO Register 6

PC FIFO Register 7

UM0434 Datasheet(PDF) 324 Page - STMicroelectronics