UM0434 datasheet(327/390 Pages) STMICROELECTRONICS

327 / 390 page

Debug support

UM0434

328/391

debug state where it is halted and awaiting single-step commands or a release to

normal mode.

Scan out the OSR value to determine that the CPU clock is running and the CPU has

entered debug state. This can be done in conjunction with a CPUSCR read. The OSR

is shifted out during the Shift-IR state. The CPUSCR is shifted out during the Shift-DR

state. The debugger should save the scanned-out value of CPUSCR for later

restoration.

Select the DBCR0 register and update it with DBCR0[EDM] set.

Clear the DBSR status bits.

Write appropriate values to the DBCR0–DBCR3, IAC, DAC, and DBCNT registers.

Note:

The initial write to DBCR0 only affects the EDM bit, so the remaining portion of the register

must now be initialized, keeping the EDM bit set.

At this point the system is ready to begin debug operations. Depending on the desired

operation, different steps must occur.

Optionally set the OCR[DMDIS] control bit to ensure that no TLB misses occur while

performing the debug operations.

Optionally ensure that the values entered into the MSR portion of the CPUSCR during

the following steps cause interrupts to be disabled (clearing MSR[EE] and MSR[CE]).

This ensures that external interrupt sources do not cause single-step errors.

To single-step the CPU:

The debugger scans in either a new or a previously saved value of the CPUSCR (with

appropriate modification of the PC and IR as described in

Chapter : Control state

The debugger scans out the OSR with no register selected, GO cleared, and

determines that the PCU has re-entered the debug state and that no ERR condition

occurred.

To return the CPU to normal operation (without disabling external debug mode):

OCR[DMDIS] and OCR[DR] should be cleared, leaving OCR[WKUP] set.

The debugger restores the CPUSCR with a previously saved value of the CPUSCR

(with appropriate modification of the PC and IR as described in

Chapter : Control state

OCR[WKUP] may then be cleared.

To exit external debug mode:

The debugger should place the CPU in the debug state through the OCR[DR] with

OCR[WKUP] set, scanning out and saving the CPUSCR.

The debugger should write to DBCR0–DBCR3 as needed, likely clearing every enable

except DBCR0[EDM].

The debugger should write the DBSR to a cleared state.

The debugger should rewrite the DBCR0 with all bits including EDM cleared.

The debugger should clear OCR[DR].

The debugger restores the CPUSCR with the previously saved value of the CPUSCR

(with appropriate modification of the PC and IR as described in

Chapter : Control state

OCR[WKUP] may then be cleared.

Note:

These steps are only examples rather than an exact template for debugger operations.

UM0434 Datasheet(PDF) 327 Page - STMicroelectronics

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