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UM0434 Datasheet(PDF) 323 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 323 Page - STMicroelectronics |
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323 / 390 page ![]() Debug support UM0434 324/391 source value of the ori instruction, thus allowing updates to processor registers to be performed. (Refer to Chapter : Control state register (CTL) on page 321,” for more details.). WBBRlower and WBBRupper are generally undefined on instructions that do not write back a result and, due to control issues, are not defined on lmw or branch instructions either. To read and write the entire 64 bits of a GPR, both WBBRlower and WBBRupper are used. For reads, an evslwi rn,rn,0 may be used. For writes, the same instruction may be used, but the CTL[FFRA] bit must be set as well. Note: MSR[SPE] must be set in order for these operations to be performed properly. Machine state register (MSR) The MSR is a 32-bit register used to read/write the machine state register (MSR). Whenever the external command controller needs to save or modify the contents of the machine state register, this register is used. This register is affected by the operations performed during debug mode and must be restored by the external command controller when returning to normal mode. Chapter 4: Register model on page 38,” further describes the MSR. 11.5.9 Instruction address FIFO buffer (PC FIFO) To assist debugging and keep track of program flow, a first-in-first-out (FIFO) buffer stores the addresses of the last eight instruction change-of-flow destinations that were fetched. These include exception vectoring to an exception handler and returns, as well as pipeline refills due to execution of the isync instruction. The PC FIFO stores the addresses of the last eight instruction change-of-flow addresses that were actually taken. The FIFO is implemented as a circular buffer containing eight 32- bit registers and one 3-bit counter. All the registers have the same address, but any read access to the FIFO address causes the counter to increment, making it point to the next FIFO register. The registers are serially available to the external command controller through the common FIFO address. Figure 71 shows the block diagram of the PC FIFO. |
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