UM0434 datasheet(320/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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Control state register (CTL)

The control state register (CTL), shown in

Table 207, stores the value of certain internal

CPU state variables before debug mode is entered. This register is affected by the

operations performed during the debug session and should normally be restored by the

external command controller when returning to normal mode. In addition to saved internal

state variables, two of the bits are used by emulation firmware to control the debug process.

In certain circumstances, emulation firmware must modify the content of this register as well

as the PC and IR values in the CPUSCR before exiting debug mode. These cases are

described more specifically in the text after the table.

Table 207.

Control state register (CTL)

Field

Internal state bits

Field PCOFSTPCINV FFRA

IRSTAT

Table 208.

CTL field definitions

Bits

Name

Description

0–15

Internal

state bits

Internal state bits.These control bits represent the internal processor state and should be

restored to their original value after a debug session is completed, that is, when a OnCE

command is issued with the GO and EX bits set and not ignored. When performing instruction

execution during a debug session (see

Chapter 11.2.1: Software debug facilities on page 296”),

these bits should be cleared.

16–19 PCOFST

PC offset field. Indicates whether the value in the PC portion of the CPUSCR must be adjusted

before exiting debug mode. Due to the pipelined nature of the CPU, the PC value must be

backed up by emulation software in certain circumstances. The PCOFST field specifies the

value to be subtracted from the original value of the PC. This adjusted PC value should be

restored into the PC portion of the CPUSCR just before exiting debug mode with a Go+Exit. In

the event the PCOFST is non-zero, the IR should be loaded with a nop instruction instead of the

original IR value; otherwise, the original value of IR should be restored (but see PCINV which

overrides this field).

0000 No correction required

0001 Subtract 0x04 from PC.

0010 Subtract 0x08 from PC.

0011 Subtract 0x0C from PC.

0100 Subtract 0x10 from PC.

0101 Subtract 0x14 from PC.

All other encodings are reserved.

PCINV

PC and IR invalid status bit. This status bit indicates that the values in the IR and PC portions of

the CPUSCR are invalid. Exiting debug mode with the saved values in the PC and IR will have

unpredictable results. Debug firmware should initialize the PC and IR values in the CPUSCR

with desired values before exiting debug mode if this bit was set when debug mode was initially

entered.

0 No error condition exists.

1 Error condition exists. PC and IR are corrupted.

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