UM0434 datasheet(322/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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command. During the debug session, the CTL register should be written with the FFRA bit

set as appropriate and all other bits cleared, and with IR set to the value of the desired

instruction to be executed.

The PCINV status bit which was originally present when debug mode was first entered

should be tested before exiting debug mode with a Go+Exit and, if set, the PC and IR

initialized for performing whatever recovery sequence is appropriate for a faulted exception

vector fetch. If the PCINV bit is cleared, the PCOFST bits should be examined to determine

whether the PC value must be adjusted. Due to the pipelined nature of the CPU, the PC

value must be backed up by emulation software in certain circumstances. The PCOFST field

specifies the value to be subtracted from the original value of the PC. This adjusted PC

value should be restored into the PC portion of the CPUSCR just before exiting debug mode

with a Go+Exit. In the event that PCOFST is non-zero, the IR should be loaded with a nop

instruction (such as ori r0,r0,0) instead of the original IR value; otherwise, the original value

of IR should be restored. Note that when a correction is made to the PC value, it generally

points to the last completed instruction, although that instruction will not be re-executed. The

nop instruction is executed instead, and instruction fetch and execution resumes at location

PC+4.

For CTL, the internal state bits should be restored to their original value. The IRStatus bits

should be cleared if the PC was adjusted. If no PC adjustment was performed, emulation

firmware should determine whether IRStat2–5 should be cleared to avoid re-entry into

debug mode for an instruction breakpoint request. On exiting debug mode with Go+Exit, if

one of these bits is set, debug mode is re-entered before any further instruction execution.

Program counter register (PC)

The PC is a 32-bit register that stores the value of the program counter that was present

when the chip entered debug mode. It is affected by the operations performed during debug

mode and must be restored by the external command controller when the CPU returns to

normal mode. PC normally points to the instruction contained in the IR portion of CPUSCR.

If debug firmware wishes to redirect program flow to an arbitrary location, the PC and IR

should be initialized to correspond to the first instruction to be executed on resumption of

normal processing. Alternatively, the IR may be set to a nop and the PC set to point to the

location before the location at which it is desired to redirect flow to. On exiting debug mode

the nop is executed, and instruction fetch and execution resumes at PC+4.

Write-Back bus register (WBBR (lower) and WBBR (upper))

WBBR provides a way to pass operand information between the CPU and the external

command controller. Whenever the external command controller needs to read the contents

of a register or memory location, it forces the chip to execute an instruction that brings that

information to WBBR. WBBRlower holds the 32-bit result of most instructions including load

data returned for a load or load with update instruction. For SPE instructions that generate

64-bit results, WBBRlower holds the low-order 32 bits of the result. WBBRupperholds the

updated effective address calculated by a load with update instruction. For SPE instructions

that generate 64-bit results, WBBRupper holds the high-order 32 bits of the result. It is

undefined for other instructions.

As an example, to read the lower 32 bits of processor register r1, an ori r1,r1,0 instruction is

executed, and the result value of the instruction is latched into WBBRlower. The contents of

WBBRlower can then be delivered serially to the external command controller. To update a

processor resource, this register is initialized with a data value to be written, and an ori

instruction is executed that uses this value as a substitute data value. The control state

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