UM0434 datasheet(326/390 Pages) STMICROELECTRONICS

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UM0434

Debug support

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11.7

MMU and cache operation during debug

Normal operation of the MMU may be modified during a debug session using the OnCE

OCR. A debug session begins when the CPU initially enters debug mode and ends when a

OnCE command with Go+Exit is executed, releasing the CPU for normal operation. If

desired during a debug session, the debug firmware may disable the translation process

and may substitute default values for the access protection (UX, UR, UW, SX, SR, SW) bits,

and values obtained from the OnCE control register and page attribute (VLE, W, I, M, G, E)

bits normally provided by a matching TLB entry. In addition, no address translation is

performed; instead, a 1:1 mapping of effective-to-real addresses is performed.

When disabled during a debug session, TLB miss or TLB-related DSI conditions cannot

occur. If the debugger desires to use the normal translation process, the MMU may be left

enabled in the OnCE OCR, and normal translation (including the possibility of a TLB miss or

DSI) remains in effect.

The OCRDMDIS, DW, DI, DM, DG, and DE control bits are used when debug mode is

entered. Refer to the bit definitions in the OCR (See

Chapter : OnCE control register (OCR)

on page 315,” for more detail). These substituted page attribute bits control cache operation

on accesses initiated during debug. No address translation is performed; instead, a 1:1

mapping between effective and real addresses is performed.

11.8

Enabling, using, and exiting external debug Mode: example

The following steps show one possible scenario for a debugger wishing to use the external

debug facilities. This simplified flow shows basic operations and does not cover all potential

methods in depth.

Enable external debug mode and initialize debug registers:

To enable OnCE operation, the debugger should ensure that the

jd_en_once is set.

Write a value to OCR in which OCR[DR] and OCR[WKUP] are set. The TAP controller

must step through the proper states as outlined earlier. This step places the CPU in a

jd_watchpt[4] DAC1(1)

Data address compare 1 watchpoint. Set whenever a DAC1 compare

occurs regardless of whether DAC1 compares are enabled to set DBSR

status.

jd_watchpt[5] DAC2(1)

Data address compare 2 watchpoint. Set whenever a DAC2 compare

occurs regardless of whether DAC2 compares are enabled to set DBSR

status.

d_watchpt[6] DCNT1

Debug counter 1 watchpoint. Set whenever debug counter 1 decrements to

zero regardless of whether DCNT1 compares are enabled to set DBSR

status.

jd_watchpt[7] DCNT2

Debug counter 2 watchpoint. Set whenever debug counter 2 decrements to

zero regardless of whether DCNT2 compares are enabled to set DBSR

status.

If the corresponding event is completely disabled in DBCR0, either load-type or store-type data accesses

are allowed to generate watchpoints, otherwise watchpoints are generated only for the enabled conditions.

Table 209.

Watchpoint output signal assignments (continued)

Signal name

Type

Description

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