UM0434 datasheet(330/390 Pages) STMICROELECTRONICS

330 / 390 page

UM0434

Nexus3 module

331/391

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Registers for program trace, data trace, ownership trace, and watchpoint trigger

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All features controllable and configurable through the JTAG port

Note:

Configuration of the message data out pins is controlled by the port control register at the

SoC level in multiple Nexus implementations. For single Nexus implementations, this

configuration is controlled by DC1 within the e200z3 Nexus3 module.

In either implementation, full port mode (FPM—maximum number of MDO pins) or reduced

port mode (RPM—minimum number of MDO pins) is supported. This setting should not be

changed while the system is running.

The configuration of the message start/end out pins, 1 or 2, is determined at the SOC

integration level. This option is hard-wired based on SOC bandwidth requirements.

Figure 72 shows the functional block diagram.

Figure 72.

Nexus3 functional block diagram

nex_mseo0_b

nex_mcko

Nexus3 Block

Nexus1 Block (within core CPU)

nex_mdo[n:0]

j_tdo

j_tdi

j_tms

j_tclk

j_trst_b

nex_evto_b

nex_rdy_b

nex_evti_b

nex_mseo1_b

N+1

nex_aux_req[1:0]

npc_aux_grant

Note: The nex_aux_req[1:0], npc_aux_grant and nex_aux_busy signals are used for inter-module

nex_aux_busy

communication in a multiple Nexus environment. They are not pins on the SoC.

ext_multi_nex_sel

Registers

DMA Registers

OnCE Debug

Breakpoint/

Watchpoint

Control

Memory

Control

Control/Status

Registers

Instruction

Snoop

I/O

Logic

Data

Snoop

DMA

(R/W)

Message

Queues

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