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Z80 Datasheet(PDF) 151 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 151 Page - Zilog, Inc. |
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151 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access CPU has relinquished the bus. Therefore, if this DMA is bus master, it samples the WAIT signal for these requests. A simple 2-input multiplexer steers the CE/WAIT signalsasdepictedin Figure 50. Using BUSACK assumes that there is only one DMA. In systems with three or more possible bus masters, BAl active and BAO inactive identify the master. Simultaneous Transfers The highest-speed DMA transfer method is the simultaneous transfer method, or flyby method. This requires some external hardware to generate simultaneous read- and write-control signals to the source and destination ports. Because the address bus is used for memory address, only transfers between I/O and memory can be accomplished directly when the I/O port selection is performed by hard wiring. The DMA is put into search mode, and a circuit, such as that illustrated in Figure 51, generates separate simul- taneous read- and write-control signals, which may be ORed into the read- and write-control paths at memory and I/O. Figure 52 depicts such an arrangement. This arrangement allows both the CPU and DMA access to the I/O peripheral. (If the peripheral communicates only through DMA, it only needs to use the IORD and IOWR signals.) Pay careful attention to access, setup, and hold times in this mode. Because the DMA is programmed to do searching, the MWR and IOWR signals are derived from the DMA RD signal and mimic its timing. This does not cause a problem for write operations, which are trailing edge activated. To make MWR appear more like a CPU or DMA write cycle signal, the circuit of Figure 50 may be used to delay the leading edge of MWR until after the falling edge in T2. The programmable variable timing features of the DMA may be useful, too. |
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