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Z80 Datasheet(PDF) 155 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 155 Page - Zilog, Inc. |
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155 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access (floated) in a manner similar to the CPU and DMA address pins. For example, in a system with one CPU and one DMA, the BUSACK signal can disable CPU buffers and enable DMA buffers when it is active. Where there are three or more potential bus masters, only those buffers associated with the actual bus master must be active at any time. Therefore, each DMA, if its BAI signal is active (Low) and its BAO signal is inactive (High), has control of the bus and can enable its drivers. Data bus lines are bidirectional, making their buffer control more compli- cated. Any device from which the CPU can read drives the data bus when it is selected and the RD control signal is active. In this sense, the RD signal is the principal directional control. Non-CPU devices also drive the data bus during interrupt-acknowledge cycles in which the device puts its vector on the bus and during DMA write cycles. Figure 54 illustrates a bidirectional data bus buffer and its control. Here, Z80 SIC, PIO, CTC, and DMA peripherals share a circuit card. Their common on-card data bus is buffered to and from the system (motherboard or backplane) bus. Each of the three conditions mentioned causes the buffers to drive data out onto the system bus; otherwise, data is buffered into the card. Suitable devices for bidirectional buffering include the 74LS241 (tristate bus drivers) and 74LS245 (transceivers). The control signals MREQ,IORQ,RD,and WR should be unidirectionally buffered in large- or multi-card systems. These signal buffers are, again, enabled when their associated device or card has bus control and are forced into high-impedance states when another master takes control of these bus lines. Because there are short intervals during transfer of the bus (when the bus is not driven by any master), MREQ,IORQ,RD,and WR should be pulled up to + 5V with 2.7 Kohms to 4.7 Kohms resistors so that they remain inactive. Other control signals on CPU and DMA may be perma- nently driven. This usually includes M1, RFSH,and HALT from the CPU, and BAO from a DMA. The BUSREQ line is bidirectional and cannot easily be externally buffered. However, the DMA can sink 3.2 mA on BUSREQ, more thanonother |
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