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Z80 Datasheet(PDF) 156 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 156 Page - Zilog, Inc. |
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156 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access signals. To maximize current, the system’s BUSREQ pull-up resistor can be as low as 1.8 Kohms. TTL buffers and drive capacitive loads While the DC output ratings of standard buffers such as the 74LS367 are usually ample, propagation times through these buffers are rated at capac- itive loadings of only 30 pF, a value easily exceeded in practice. Capacitive loading thus usually dominates bus driving requirements. Z80 Family parts are specified over ranges of capacitive loading. The load seen by a device driving a bus line has components due to wiring and printed circuit land capacitance, connector capacitance, and capaci- tances of inputs and outputs connected to the signal. A standard low-power Schottky (LS) TTL input presents about 6 pF of capacitive load, an LS output of about 8 pF. Most other input and output capacitances can be esti- mated from device data sheets, but capacitance associated with intercon- nection may vary markedly. Sometimes, propagation delays and allowable capacitive loading for buffered lines must be determined by measurement or by trial and error. |
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