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Z80 Datasheet(PDF) 148 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 148 Page - Zilog, Inc. |
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148 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access up. A complementary-transistor driver for Z80/Z8000 systems is depicted in Figure 48. Chip Selection and Enabling Z80 peripherals are normally addressed in the 256 address I/O space. Each peripheral Chip is enabled by an active-low Chip Enable (CE) input. The CE input becomes active when an active IORQ signal coincides with the peripheral’s address on the low order byte of the address bus. Small systems may dedicate address lines to their few peripherals, making decoder hardware unnecessary. A system using DMA, however, usually has more peripherals, so that address decoding by means of PROM or MSI TTL decoder is normally provided. Figure 48. Z80/Z8000 Clock Driver Figure 49 illustrates three chip enable arrangements in a small system. In it, the DMA responds to half of the 256 possible I/O addresses. In (Figure 49b), a 256 x 4 PROM is programmed to provide a Low output on the 01 pin only when the DMA’s address is present. The PROM must respond quickly to meet the DMA’s CE setup time requirement. +5V TTL 0.01 µF 10K (max) Clock 2N5772 or 2N3646 120 470 470 240 22 22 2N5771 or 2N3546 |
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