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Z80 Datasheet(PDF) 149 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 149 Page - Zilog, Inc. |
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149 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Figure 49c depicts a one-of-eight TTL decoder which provides chip enable signals for eight different peripheral devices. Address bits A0 and A1 are often used directly by peripherals such as the Z80 SIO, PIO, and CTC, and so are not decoded here. Additional decoders can be added when more peripheral devices are present. IORQ and M1 are internally gated with CE in Z80 peripheral devices and need not be terms in CE. However, gating chip-enable signals with these control lines do no harm and may produce less-ambiguous logic sequences for circuit-level debugging, as seen in Figure 49c. |
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