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Z80 Datasheet(PDF) 177 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 177 Page - Zilog, Inc. |
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177 / 330 page ![]() < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access inactive, are caused by the activity on the BUSREQ and BAI lines, which is explained later. Search-Only The standard timing for search-only operations is identical to the read cycles of Figure 61 and Figure 62. Search-only is equivalent to read-only. Data is read to a DMA register for comparison with the match byte. Bus Requests Figure 65 illustrates the bus request and acceptance timing. The RDY line, which may be programmed active High or Low, is sampled on every rising edge of CLK. If the RDY line is active, and if the bus is not in use by any other device, the following rising edge of CLK drives BUSREQ Low. After receiving BUS- REQ the CPU acknowledges on its BUSACK, which is connected to the DMA’s BAI input either directly or through a multiple-DMA daisy-chain. The CPU checks its BUSREQ input one clock cycle before the end of each CPU machine cycle. If the CPU detects a request, it releases the bus at the end of that same machine cycle. The maximum time delay between the CPU receiving BUSREQ and the response on its BUSACK line is one machine cycle plus slightly less than one clock cycle. The CPU tristates all its bus control lines when it acknowledges on the BUSACK line. M1 is not tristated. The RDY line, which has a specified setup time with respect to a rising edge of CLK, must remain active until after the DMA becomes bus master in Byte or Burst modes. |
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