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Z80 Datasheet(PDF) 181 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 181 Page - Zilog, Inc. |
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181 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access search (Figure 69). The action on BUSREQ is thus somewhat delayed from action on the RDY line. The DMA always completes the current byte oper- ation in an orderly fashion before releasing the bus. Figure 69. Bus Release on Not Ready (Burst Mode) By contrast, BUSREQ is not released in Continuous mode when RDY goes inactive. Instead, the DMA idles after completing the current byte opera- tion, awaiting an active RDY again. Figure 70, Figure 71, and Figure 72 review the relationship between the Ready line going inactive and the state of the other lines for each mode of operation, assuming a search-only of memory using standard Z80 timing. The timing for Ready coming active is discussed under Bus Request. RDY is sampled on the rising edge of CLK in the last clock cycle of each read or write cycle. It is a level-sample, not an edge-sample. RDY can go inactive prior to the completion of the last byte operation without disturbing that operation. At the end of that operation, the BUSREQ and BAI lines go High in Byte or Burst mode according to Figure 68 and Figure 71. The bus control lines MREQ,IORQ,RD,and WR, also remain High in Byte and Burst mode during an inactive RDY, with both the address and data buses tristated. The Continuous mode (Figure 72) is different because the address bus holds the pre incremented address for the next byte throughout the time that RDY is inactive. This address is immediately available when RDY comes active again. BUSREQ RDY DMA Inactive Active Inactive CLK Current Byte Operation |
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