Electronic Components Datasheet Search
  English  ▼

X  

Z80 Datasheet(PDF) 178 Page - Zilog, Inc.

Part # Z80
Description  Z80 CPU PERIPHERALS
PDF  330 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z80 Datasheet(HTML) 178 Page - Zilog, Inc.

Back Button Z80 Datasheet HTML 174Page - Zilog, Inc. Z80 Datasheet HTML 175Page - Zilog, Inc. Z80 Datasheet HTML 176Page - Zilog, Inc. Z80 Datasheet HTML 177Page - Zilog, Inc. Z80 Datasheet HTML 178Page - Zilog, Inc. Z80 Datasheet HTML 179Page - Zilog, Inc. Z80 Datasheet HTML 180Page - Zilog, Inc. Z80 Datasheet HTML 181Page - Zilog, Inc. Z80 Datasheet HTML 182Page - Zilog, Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 178 / 330 page
background image
<%27 2GTKRJGTCNU
7UGT /CPWCN
UM008101-0601
Direct Memory Access

Figure 65.
Bus Request and Acceptance Timing
Continuous mode is the only instance when a pulse on RDY allows the
DMA to become bus master.In this event, the DMA becomes bus master
but does not begin operations.
When the DMA detects a Low on BAI for two consecutive rising edges of
CLK, the DMA begins transferring data on the next rising edge of CLK.
In Byte mode, after each byte is transferred, the DMA waits until its BAI
line goes inactive before requesting the bus again on BUSREQ for the next
byte transfer. This feature allows a minimum of one CPU machine cycle to
occur between each byte transferred.
Bus Release Byte-at-a-Time
In Byte mode, BUSREQ is brought High on the rising edge of CLK prior to
the end of each read cycle (search-only) or write cycle (transfer and trans-
fer/search) as illustrated in Figure 66. This action occurs regardless of the
state of RDY. There is no possibility of confusion when a Z80 CPU is used
because the CPU cannot begin an operation until the following clock cycle.
Nor does this condition affect most other CPUs. The result of timing is one-
clock-cycle less time needed for a byte transfer.
BUSREQ
RDY
Active
Inactive
DMA
Inactive
DMA
Active
BAI
CLK
Note: RDY is detected as a level, not an edge



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com