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Z80 Datasheet(PDF) 217 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 217 Page - Zilog, Inc. |
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217 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Parallel Input/Output INTERRUPT SERVICING After an interrupt is requested by the PIO, the CPU sends out an interrupt acknowledge (M1 and IORQ). During this time, the interrupt logic of the PIO determines which port has the highest priority interrupt. (This is a device which has an Interrupt Enable Input High and an Interrupt Enable Output Low). To insure that the daisy-chain enable lines stabilize, devices are inhibited from changing their interrupt request status when M1 is active. The highest priority device places the contents of its interrupt vector register onto the Z80 data bus during interrupt acknowledge. Figure 11 illustrates the timing associated with interrupt requests. During M1 time, no new interrupt requests can be generated. This allows time for the lnt Enable signals to ripple through up to four PIO circuits. The PIO, with IEI High and IEO Low during INTA, places the 8-bit interrupt vector of the appropriate port on the data bus at this time. If an interrupt requested by the PIO is acknowledged, the requesting port is under service. The IEO of this port remains low until a return from interrupt instruction (RETI) is executed, during which time the IEI of the port is High. If an interrupt request is not acknowledged, IEO is forced High for one M1 cycle after the PIO decodes the Op Code ED. This action guarantees that the 2-byte RETI instruction is decoded by the correct PIO port (Figure 12). Figure 13 illustrates a typical nested interrupt sequence that could occur with four ports connected in the daisy-chain. In this sequence, Port 2A requests and is granted an interrupt. While this port is being serviced, a higher priority port (1B) requests and is granted an interrupt. The service routine for the higher priority port is completed and a RETI instruction is executed, indicating to the port that its routine is complete. The service routine of the lower priority port is then complete. |
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