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Z80 Datasheet(PDF) 216 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 216 Page - Zilog, Inc. |
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216 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Parallel Input/Output When reading the PIO, the data returned to the CPU is composed of output register data from port data lines assigned as outputs and input register data from port data lines assigned as inputs. The input register contains data that was present immediately prior to the falling edge of RD. See Figure 10. An interrupt is generated if interrupts from the port are enabled and the data on the port data lines satisfies the logical equation defined is not generated until a change occurs in the status of the logical equation. A Mode 3 interrupt is generated only when the result of a Mode 3 logical operation changes from false to true. For example, Mode 3 logical equa- tion is an OR function. An unmasked port data line becomes active and an interrupt is requested. If a second unmasked port data line becomes active concurrently with the first, a new interrupt is not requested because a change in the result of the Mode 3 logical operation has not occurred. If the result of a logical operation becomes true immediately prior to or during M1 an interrupt is requested after the trailing edge of M1 Figure 10. Control Mode (Mode 3) Timing Φ Data In Data Word 1 Data Word 2 Data Match Occurs Here T1 T2 TW*T3 *Timing Diagram Refers to Bit Mode Read D7–D0 RD IORQ INT Port Data Bus Data Word 1Placedon Bus |
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