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Z80 Datasheet(PDF) 212 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 212 Page - Zilog, Inc. |
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212 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Parallel Input/Output Only port lines whose mask bit is zero are monitored for generating an interrupt. When IORQ is high, the forced state of Ready prevents input register data from changing while the CPU is reading the PIO. Ready goes High again after the trailing edge of the IORQ, as previously described TIMING Output Mode (Mode 0) Figure 7 illustrates the timing associated with Mode 0 operation. An output cycle is always started by the execution of an output instruction by the CPU. A WR * pulse is generated by the PIO during a CPU I/O write opera- tion and is used to latch the data from the CPU data bus to the addressed ports (A or B) output register. The rising edge of the WR* pulse then raises the Ready flag after the next falling edge of Φ, indicating that data is avail- able for the peripheral device. In most systems, the rising edge of the Ready signal can be used as a latching signal in the peripheral device. The Ready signal remains active until: (1) a positive edge is received from the strobe line, indicating that the peripheral has taken the data, or (2) if already active, Ready is forced low for one and one-half Φ cycles after the leading edge of IORQ, but only if the port’s output register is written to. Ready returns High on the first falling edge of Φ after the trailing edge of IORQ. This guarantees that Ready is low when port data is changing. The Ready signal does not go inactive until a falling edge occurs on the clock ( Φ) line. The purpose of delaying the negative transition of the Ready signal until after a negative clock transition is to allow a simple generation scheme for the strobe pulse. By connecting the Ready line to the Strobe line, a strobe with a duration of one clock period is generated with no other logic required. The positive edge of the strobe pulse automatically generates an INT request when the interrupt enable flip-flop has been set and this device is the highest priority device requesting an interrupt. |
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