Z80 datasheet(263/330 Pages) ZILOG

263 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

243

WR0

Pointer 5

Status affects vector (Channel B

only). Transmit CRC Enable should

be set when first non-sync data is

sent to Z80 SIO. Need several sync

characters in the beginning of

message. Transmitter is fully

initialized.

WR5

Request To Send, Transmit Enable, Bisync

CRC, transmit character length first Sync

Byte To SIO

Idle Mode

Execute Halt Instruction or some other

program

Waiting for interrupt or WAIT/

READY output to transfer data.

Data Transfer and

Status Monitoring

When Interrupt (WAIT/READY) occurs:

Interrupt Occurs (Wait/ready

Becomes Active) When first data

byte is being sent, Wait Mode allows

CPU block transfer from memory to

SIO; Ready Mode allows DMA

block transfer from memory to SIO.

The DMA chip can be programmed

to capture special control characters

(by examining only the bits that

specify ASCII or EBCDIC control

characters), and interrupt CPU.

• Include/Exclude data byte from CRC

Accumulation (in SIO)

• Transfer data byte from CPU (or

memory) to SIO

• Detect and set appropriate flags for

control characters (in CPU)

• Reset Tx Underrun/EOM Latch WR0 if

last character of message is detected

• Update pointers and parameters (CPU)

Return from Interrupt

If Error Condition Or Status Change

Occurs:

Tx Underrun/EOM indicates either

Transmit Underrun (sync character

being sent) or end of message (CRC-

16 being sent).

• Transfer RR0 to CPU

• Execute Error Routine

• Return From Interrupt

Termination

Redefine Interrupt Modes, Update Modem

Control outputs (for example, turn off

RTS)

Program should gracefully terminate

message

Disable Transmit Mode

Table 6. Bisync Transmit Mode (Continued)

Function

Typical Program Steps

Comments

Z80 Datasheet(PDF) 263 Page - Zilog, Inc.

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