| Electronic Components Datasheet Search |
|
Z80 Datasheet(PDF) 265 Page - Zilog, Inc. |
|
|
|||||||||||||||||||||||||||||
Z80 Datasheet(HTML) 265 Page - Zilog, Inc. |
|
265 / 330 page ![]() Z80 CPU Peripherals User Manual UM008101-0601 Serial Input/Output 245 In this phase, there are several combinations of data transfers using inter- rupts and Wait/Ready status. Data Transfer Using Interrupts If the Transmit Interrupt Enable bit (WR1, D1) is Set, an interrupt is gener- ated each time the transmit buffer becomes empty. The interrupt can be satisfied either by writing another character to the transmitter or by reset- ting the Transmitter Interrupt Pending latch with a Reset Transmitter Pending command (WR0, CMD5). If the interrupt is satisfied with this command and nothing more is written to the transmitter, there can be no further Transmit Buffer Empty interrupts, because it is the process of the buffer becoming empty that causes the interrupts and the buffer cannot become empty when it is already empty. This situation does cause a Transmit Underrun condition, which is explained in the ““Bisync Transmit Underrun” on page 245” section. Data Transfer Using WAIT/READY To the CPU, the activation of WAIT indicates that the Z80 SIO is not ready to accept data and that the CPU must extend the output cycle. To a DMA controller, READY indicates that the transmit buffer is empty and that the Z80 SIO is ready to accept the next data character. If the data character is not loaded to the Z80 SIO by the time the transmit shift register is empty, the Z80 SIO enters the Transmit Underrun condition. Bisync Transmit Underrun In Bisync protocol, filler characters are inserted to maintain synchroniza- tion when the transmitter has no data to send (Transmit Underrun condi- tion). The Z80 SIO has two programmable options for resolving this situation: it can insert sync characters, or it can send the CRC characters generated so far, followed by sync characters. These options are under the control of tile Reset Transmit Underrun/EOM Command in WR0. Following a chip or channel reset, the Transmit Underrun/EOM status bit (RR0, D6) is in a set condition and allows the |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |