Z80 datasheet(261/330 Pages) ZILOG

261 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

241

Monosync mode, the transmitter transmits from WR6; the receiver

compares against WR7.

In the Monosync, Bisync, and External Sync modes, assembly of received

data continues until the Z80 SIO is reset, or until the receiver is disabled (by

command or by DCD in the Auto Enables mode), or until the CPU sets the

Enter Hunt Phase bit.

After initial synchronization has been achieved, the operation of the Mono-

sync, Bisync, and External Sync modes is similar. Any differences are spec-

ified in the following text.

Table 5 describes how WR3, WR4, and WR5 are used in synchronous

receive and transmit operations. WR0 points to other registers and issues

various commands, WR1 defines the interrupt modes, WR2 stores the

interrupt vector, and WR6 and WR7 store sync characters. Table 6 illus-

trates the typical program steps that implement a half-duplex Bisync

transmit operation.

Table 5. Contents of Write Registers 3, 4, and 6 In Synchronous Modes

Bit7

Bit 6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

00 = Ax 5 Bits/char

10 = Rx 6 Bits/char

01 = Rx 7 Bits/char

11 = Rx8Bits/char

Auto

Enables

Enter Hunt

Mode

Rx CRC

Enable

Sync char

load

inhibit

Enable

00 = 8-bit Sync Char

01 = 16-bit Sync Char

10 = SDLC Mode

11 = Ext Sync Mode

Selects

Sync

Modes

Selects

Sync

Modes

Even/Odd

Parity

Enable

DTR

00= Tx 5Bits (or less)/

char

10 = Tx 6 Bits/char

01 = Tx 7 Bits/char

11 = Tx 8 Bits/char

Send

Break

Tx Enable 1

Selects

CRC-16

RTS

Tx CRC

Enable

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