Z80 datasheet(257/330 Pages) ZILOG

257 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

237

After the Parity Error and Receive Overrun Error flags are latched, the error

status that is read indicates an error in the current word in the receive buffer

plus any Parity or Overrun Errors received after the last Error Reset

command. To keep correspondence between the state of the error buffers

and the contents of the receive data buffers, the error status register must be

read before the data. This is easily accomplished if vectored interrupts are

used, because a special interrupt vector is generated for these conditions.

While the External/Status interrupt is enabled, break detection causes an

interrupt and the Break Detected status bit (RR0, D7) is set. The Break

Detected interrupt should be responded to by issuing the Reset External/

Status Interrupt command to the Z80 SIO in response to the first Break

Detected interrupt that has a Break status of 1 (RR0, D7). The Z80 SIO

monitors the Receive Data input and waits for the Break sequence to

terminate, at which time the Z80 SIO interrupts the CPU with the Break

status set to 0. The CPU must again issue the Reset External/Status Inter-

rupt command in its interrupt service routine to reinitialize the break

detection logic.

The External/Status interrupt also monitors the status of DCD.If the DCD

pin becomes inactive for a period greater than the minimum specified

pulse width, an interrupt is generated with the DCD status bit (RR0, D3)

set to 1. The DCD input is inverted in the RR0, status register.

If the status is read after the data, the error data for the next word is also

included if it has been stacked in the buffer. If operations are performed

rapidly enough so the next character is not yet received, the status register

remains valid. An exception occurs when the Interrupt On First Character

Only mode is selected. A special interrupt in this mode holds the error

data and the character itself (even if read from the buffer) until the Error

Reset command is issued. This interrupt prevents further data from

becoming available in the receiver until the Reset command is issued, and

allows CPU intervention on the character with the error even if DMA or

block transfer techniques are in use.

If Interrupt On Every Character is selected, the interrupt vector is different

an error status occurs in RR1. If a Receiver Overrun occurs, the most recent

Z80 Datasheet(PDF) 257 Page - Zilog, Inc.