Z80 datasheet(254/330 Pages) ZILOG

254 / 330 page

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

234

WR5

Request to send, transmit enable, transmit

character length, data terminal ready

Receive and Transmit both

fully initialized. Auto Enables

enables transmitter if CTS is

active and receiver if DCD is

active

WR0

Pointer 1, Reset External/Status Interrupt

WR1

Transmit Interrupt Enable, Status Affects

Vector,

Interrupt on all Receive characters. Disable

Wait/Ready function, External Interrupt Enable

Transmit/receive Interrupt

Mode Selected.

External Interrupt monitors the

status of the CTS,DCD,and

SYNC inputs and detects the

Break sequence. Status affects

Vector In Channel B only. This

data byte must be transferred or

no transmit interrupts occur.

Transfer first data byte to SIO

Idle Mode

Execute Halt Instruction or other program

Program is waiting for an

interrupt from the SIO

Data transfer and

error monitoring

Z80 Interrupt Acknowledge cycle transfers

RR2 to CPU

When the interrupt occurs, the

interrupt vector is modified by:

1) Receive character available;

2) Transmit buffer empty;

3) External/status change; and

4) Special receive condition.

If a character is received:

• Transfer data character to CPU

• Update pointers and parameters

• Return from Interrupt

If transmitter buffer is empty:

Program control is transferred

to one of the eight Interrupt

Service routines.

• Transfer data character to SIO

• Update pointers and parameters

• Return from interrupt

Table 4. Asynchronous Mode (Continued)

Function

Typical Program Steps

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Z80 Datasheet(PDF) 254 Page - Zilog, Inc.

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