Z80 datasheet(255/330 Pages) ZILOG

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Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

235

Asynchronous Receive

An Asynchronous Receive operation begins when the Receive Enable bit is

set. If the Auto Enables option is selected, DCD must be Low. A Low

(spacing) condition on the Receive Data input (RxD) indicates a start bit. If

this Low persists for at least one-half of a bit time, the start bit is assumed to

be valid and the data input is then sampled at mid-bit time until the entire

character is assembled. This method of detecting a start bit improves error

rejection when noise spikes exist on an otherwise marking line.

If the x1 clock mode is selected, bit synchronization must be accom-

plished externally. Receive data is sampled on the rising edge of RxC.

The receiver inserts 1s when a character length of other than eight bits is

If External Status changes:

If used with processors other

than the Z80, the modified

interrupt vector (RR2) should

be returned to the CPU in the

interrupt acknowledge

sequence.

• Transfer RRD to CPU

• Perform Error routines (include Break

detection)

• Return from Interrupt

If special receive condition occurs:

• Transfer RR1toCPU

• D6 Special Error (such as framing error)

routine

• Return from Interrupt

Termination

Redefine Receive/Transmit Interrupt modes

Disable Transmit/Receive modes

When Transmit or Receive

Data transfer is complete.

Update modem control outputs (such as RTS

off)

In Transmit, the all sent status

bit indicates transmission is

complete.

Table 4. Asynchronous Mode (Continued)

Function

Typical Program Steps

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