Z80 datasheet(252/330 Pages) ZILOG

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

232

Asynchronous Transmit

The Transmit Data output (TxD) is held marking (High) when the trans-

mitter has no data to send. Under program control, the Send Break (WR5,

D4) command can be issued to hold TxD spacing (Low) until the

command is cleared.

The Z80 SIO automatically adds the start bit, the programmed parity bit

(odd, even, or no parity), and the programmed number of stop bits to the

data character to be transmitted. When the character length is six or seven

bits, the unused bits are automatically ignored by the Z80 SIO. If the char-

acter length is five bits or less, refer to the table in the Write Register 5

description (Z80 SIO Programming section) for the data format.

Serial data is shifted from TxD at a rate equal to 1, 1/16th, 1/32nd, or 1/64th

of the clock rate supplied to the Transmit Clock input TxC Serial data is

shifted out on the falling edge of TxC.

If set, the External/Status Interrupt mode monitors the status of DCD,CTS,

and SYNC throughout the transmission of the message. If these inputs

change for a period of time greater than the minimum specified pulse

width, the interrupt is generated. In a transmit operation, this feature is used

to monitor the modem control signal CTS.

Table 3. Contents of Write Registers 3, 4, and 5 in Asynchronous Modes

Bit 7

Bit 6

Bit 5

Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

WR3 00= Rx 5Bits/Char

10 = Rx 6 Bits/Char

01 = Rx 7 Bits/Char

11 = Rx8Bits/Char

Auto

Enables

Enable

WR4 00 = x1 Clock Mode

01 = x16 Clock Mode

10 = x32 Clock Mode

11 = x64 Clock Mode

00 = Not Used

01 = 1 Stop Bit/Char

10 = 1-1/2 Stop Bits/

Char

11 = 2 Stop Bits/Char

Even/

Odd

Parity

Enable

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