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Z80 Datasheet(PDF) 268 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 268 Page - Zilog, Inc. |
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268 / 330 page ![]() <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Serial Input/Output 248 Transmit Transparent Mode Transparent mode (Bisync protocol) operation is made possible by the ability to change Transmit CRC Enable on the fly and by the additional capability of inserting 16-bit sync characters. Exclusion of IDLE characters from CRC calculation can be achieved by disabling CRC calculation immediately preceding the IDLE character transfer to the Z80 SIO. In the case of a Transmit Underrun condition in the Transparent mode, a pair of DLE-SYN characters are sent. The Z80 SIO can be programmed to send the DLE-SYN sequence by loading a IDLE character to WR6 and a sync character to WR7. Transmit Termination The Z80 SIO is equipped with a special termination feature that maintains data integrity and validity. If the transmitter is disabled while a data or sync character is being sent, that character is sent as usual, but is followed by a marking line rather than CRC or sync characters. When the transmitter is disabled, a character in the buffer remains in the buffer. If the transmitter is disabled while CRC is being sent, the 16-bit transmission is completed, but sync is sent instead of CRC. A programmed break is effective as soon as it is written to the control register; therefore, characters in the transmit buffer and shift register are lost. In all modes, characters are sent with the least-significant bits first. This requires right justification of transmitted data if the word length is less than eight bits. If the word length is five bits or less, the special technique described in the Write Register 5 discussion (Z80 SIO Programming section) must be used for the data format. The states of any unused bits in a data character are irrelevant except when in the Five Bits Or Less mode. If the External/Status Interrupt Enable bit is set, transmitter conditions such as “starting to send CRC characters,”“starting to send sync characters,” and CTS changing state cause interrupts that have a unique vector if Status Affects Vector is set. This interrupt mode may be used during block transfers. |
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