Z80 datasheet(270/330 Pages) ZILOG

270 / 330 page

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

250

tions are detected. The mode is reinitialized with the Enable Interrupt On

Next Receive Character command to allow the next character received to

generate an interrupt. Parity errors do not cause interrupts in this mode, but

End-of-Frame (SDLC mode) and Receive Overrun do.

If External/Status interrupts are enabled, they may interrupt any time DCD

changes state.

Interrupt On Every Character

Whenever a character enters the receive buffer, an interrupt is generated.

Error and Special Receive conditions generate a special vector if Status

Affects Vector is selected. Optionally, a Parity Error may be directed not to

generate the special interrupt vector.

Special Receive Condition Interrupts

The Special Receive Condition interrupt can occur only if either the

Receive Interrupt On First Character Only or Interrupt On Every Receive

Character modes is also set. The Special Receive Condition interrupt is

caused by the Receive Overrun error condition. Since the Receive Overrun

and Parity error status bits are latched, the error status-when read-reflects

an error in the current word in the receive buffer in addition to any Parity or

Overrun errors received after the last Error Reset command. These status

bits can only be reset by the Error reset command.

CRC Error Checking and Termination

A CRC error check on the receive message can be performed on a per char-

acter basis under program control. The Receive CRC Enable bit (WR3, D3)

must be set/reset by the program before the next character is transferred

from the receive shift register to the receive buffer register. This ensures

proper inclusion or exclusion of data characters in the CRC check.

To allow the CPU ample time to enable or disable the CRC check on a

particular character, the Z80 SIO calculates CRC eight bit times after the

character has been transferred to the receive buffer. If CRC is enabled

Z80 Datasheet(PDF) 270 Page - Zilog, Inc.