Z80 datasheet(274/330 Pages) ZILOG

274 / 330 page

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

254

Data Transfer And

Status Monitoring

When Interrupt on first character

occurs, the CPU performs the

following:

During the hunt mode, the SIO detects

two contiguous characters to establish

synchronization. The CPU establishes

the DMA Mode and all subsequent data

characters are transferred by the DMA

controller. The controller is also

programmed to capture special

characters (by examining only the bits

that specify ASCII or EBCDIC control

characters) and interrupt the CPU upon

detection. In response, the CPU

examines the status or control characters

and takes appropriate action, such as

CRC enable update.

• Transfers data byte to CPU

• Detects and sets appropriate flags for

control characters (in CPU)

• Includes/Excludes data byte in CRC

checker

• Updates pointers and other

parameters

• Enables Wait/Ready for DMA

operation

• Enables DMA controller

• Returns from Interrupt

When Wait/Ready becomes active, the

DMA controller performs the

following:

• Transfers Data Byte to memory

• Interrupts CPU if a special character

is captured by the DMA controller

• Interrupts the CPU if the last

character of the message is detected

For Message Termination, the CPU

performs the following:

The SIO interrupts the CPU for error

condition, and the error routine aborts

the present message, clears the error

condition, and repeats the operation.

• Transfers RR1 to the CPU

• Sets Ack/Nak Reply Flag based on

CRC result

• Updates pointers and parameters

• Returns from Interrupt

Table 7. Bisync Receive Mode (Continued)

Function

Typical Program Steps

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Z80 Datasheet(PDF) 274 Page - Zilog, Inc.

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