Z80 datasheet(278/330 Pages) ZILOG

278 / 330 page

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

258

information field may be sent to the Z80 SIO using the Transmit Interrupt

mode. The Z80 SIO transmits the Frame Check sequence using the

Transmit Underrun feature.

When the transmitter is first enabled, it is already empty and cannot then

become empty. Therefore, no Transmit Buffer Empty interrupts can occur

until after the first data character is written.

Data Transfer Using WAIT/READY

When the Wait/Ready function is selected, WAIT communicates to the

CPU that the Z80 SIO is not ready to accept the data and that the CPU must

extend the I/O cycle. To a DMA controller, READY communicates that the

transmitter buffer is empty and that the Z80 SIO is ready to accept the next

character. If the data character is not loaded to the Z80 SIO by the time the

transmit shift register is empty, the Z80 SIO enters the Transmit Underrun

condition. Address, control, and information fields may be transferred to

Table 8. Contents of Write Registers 3, 4, and 5 in SDLC Modes

Bit 7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

00 = Rx 5 Bits Char

10 = Rx 6 Bits Char

01 = Rx 7 Bits Char

11 = Rx 8 Bits Char

Auto

Enables

Enter Hunt

Mode (if

incoming

data not

needed)

Rx CRC

Enable

Address

Mode

0Rx

Enable

Selects

SDLC

Mode

Selects

SDLC

Mode

DTR

00 = Tx5Bits (or less)

Char

10 = Tx6Bits Char

01 = Tx7Bits Char

11 = Tx 8 Bits Char

Tx Enable 0

Selects

SDLC

CRC

RTS

Tx CRC

Enable

Z80 Datasheet(PDF) 278 Page - Zilog, Inc.

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