Z80 datasheet(281/330 Pages) ZILOG

281 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

261

7. The CPU immediately issues a Send Abort Command WR0 to the

Z80 SIO.

8. The Z80 SIO sends the Abort sequence by destroying whatever data

(CRC, data, or flag) is being sent.

As this sequence describes, the CPU has a protection of 22 minimum and

30 maximum transmit clock cycles.

SDLC CRC Generation

Reset the CRC generator to all 1s at the beginning of each frame before

CRC accumulation begins. Actual accumulation begins when the program

sends the address field (eight bits) to the Z80 SIO. Although the Z80 SIO

automatically transmits one flag character following the Transmit Enable,

send a few more flag characters ahead of the message to ensure that char-

acter synchronization occurs at the receiving end. Synchronization is

accomplished by externally timing out after enabling the transmitter, and

before loading the first character.

The Transmit CRC Enable (WR5, D0) must be enabled before sending the

address field. In the SDLC mode, all the characters between the opening

and closing flags are included in CRC accumulation, and the CRC gener-

ated in the Z80 SIO transmitter is inverted before it is sent on the line.

Transmit Termination

If the transmitter is disabled while a character is being sent, that Character

(data or flag) is sent, but is followed by a marking line rather than CRC or

flag characters.

A character in the buffer while the transmitter is disabled, remains in the

buffer; however, a programmed Abort sequence executes when it is written

to the control register. Characters being transmitted, if any, are lost. In the

case of CRC, the 16-bit transmission is completed if the transmitter is

disabled; however, flags are sent in place of CRC.

Z80 Datasheet(PDF) 281 Page - Zilog, Inc.