Z80 datasheet(283/330 Pages) ZILOG

283 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

263

WR4

Parity Information, SDLC

Mode, X1 Clock Mode

WR0

Pointer 1. Reset External/Status

Interrupts

WR1

External Interrupt Enable,

Status Affects Vector, Transmit

Interrupt Enable or Wait/Ready

Mode Enable

The External Interrupt Mode monitors the

status of the CTS and DCD inputs, as well as

the status of Tx Underrun/EOM Latch.

Transmit Interrupt interrupts when the transmit

butter becomes empty; the Wait/Ready mode

canbe used totransferdata ona DMAor block

transfer basis. The first Interrupt occurs when

CTS becomes active, at which time flags are

transmitted by the Z80 SIO. The first data byte

(address field) can be loaded in the Z80 SIO

after this interrupt. Flags cannot be sent to the

Z80 SIO as data. Status Affects Vector used in

Channel B only.

WR0

Pointer 5

WR5

Transmit CRC Enable, Request

to Send, SDLC-CRC Transmit

Enable, Transmit Word Length,

Data Terminal Ready

SDLC-CRC Mode must be defined before

initializing Transmit CRC Generator

WR0

Reset Transmit CRC Generator Initialize CRC Generator to all 1s

Idle Mode

Execute Halt Instruction or

some other program

Waiting for Interrupt or Wait/Ready output to

transfer data

Table 9. SDLC Transmit Mode (Continued)

Function

Typical Program Steps

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