Z80 datasheet(279/330 Pages) ZILOG

279 / 330 page

Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

259

the Z80 SIO with this mode using the Wait/Ready function. The Z80 SIO

transmits the Frame Check sequence using the Transmit Underrun feature.

SDLC Transmit Underrun/End of Message

SDLC-like protocols do not have provisions for fill characters within a

message. The Z80 SIO therefore automatically terminates an SDLC frame

when the transmit data buffer and output shift register have no more bits to

send. It does this by first sending the two bytes of CRC followed by one or

more flags. This technique allows very high-speed transmissions under

DMA or CPU block I/O control without requiring the CPU to respond

quickly to the end of message condition.

The Z80 SIO response to the underrun condition depends on the state of the

Transmit Underrun/EOM command. Following a reset, the Transmit

Underrun/EOM status bit is in the set state and prevents the insertion of

CRC characters while there is no data to send. Consequently, flag charac-

ters are sent. The Z80 SIO starts sending the frame while data is written to

thetransmit buffer. Between thetimethe first databyteis written and the

end of the message, the Reset Transmit Underrun/EOM Command must be

issued. Thus the Transmit Underrun/EOM status bit is in the reset state at

the end of the message (when underrun occurs), which automatically sends

the CRC characters. The sending of CRC again sets the Transmit/Underrun/

EOM status bit.

Although there is no restriction about when the Transmit Underrun/EOM

bit can be reset within a message, the reset usually occurs after the first data

character (secondary address) is sent to the Z80 SIO. Resetting this bit

allows CRC and flags to be sent when there is no data to send, allowing

additional time for the CPU to recognize the fault and respond with an abort

command. By resetting this bit early in the message, the entire message is

allotted the maximum amount of CPU response time in an unintentional

transmit underrun situation.

When the External/Status interrupt is set and while CRC is sent, the

Transmit Underrun/EOM bit is set and the Transmit Buffer Empty bit is

reset to indicate that the transmit register is full of CRC data. When CRC

Z80 Datasheet(PDF) 279 Page - Zilog, Inc.