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DP83256 Datasheet(PDF) 44 Page - National Semiconductor (TI) |
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DP83256 Datasheet(HTML) 44 Page - National Semiconductor (TI) |
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44 / 144 page  50 Registers (Continued) 52 CONFIGURATION REGISTER (CR) The Configuration Register controls the Configuration Switch Block and enablesdisables both the A and B ports The CR can be used to create a number of Configuration Loopback paths The CR is conditionally writable because the TTCR can be writing a new value into the register if this feature is enabled Note that the A Request and B Indicate port are offered only on the DP83257 and not in the DP83256 For further informa- tion refer to section 34 CONFIGURATION SWITCH ACCESS RULES ADDRESS READ WRITE 01h Always Conditional D7 D6 D5 D4 D3 D2 D1 D0 BIE AIE TRS1 TRS0 BIS1 BIS0 AIS1 AIS0 Bit Symbol Description D0 D1 AIS0 AIS1 A INDICATE SELECTOR k0 1l The A Indicate Selector k0 1l bits selects one of the four Configuration Switch data buses for the A Indicate output port (AIP AIC AIDk70l) AIS1 AIS0 0 0 PHY Invalid Bus 0 1 Receiver Bus 10A Request Bus 11B Request Bus D2 D3 BIS0 BIS1 B INDICATE SELECTOR k0 1l The B Indicate Selector k0 1l bits selects one of the four Configuration Switch data buses for the B Indicate output port (BIP BIC BIDk70l) BIS1 BIS0 0 0 PHY Invalid Bus 0 1 Receiver Bus 10A Request Bus 11B Request Bus Note Even though this bit can be set andor cleared in the DP83256 it will not affect any IOs since the DP83256 does not offer a B Indicate port D4 D5 TRS0 TRS1 TRANSMIT REQUEST SELECTOR k0 1l The Transmit Request Selector k0 1l bits select one of the four Configuration Switch data buses for the input to the Transmitter Block TRS1 TRS0 0 0 PHY Invalid Bus 0 1 Receiver Bus 10A Request Bus 11B Request Bus Note If the PLAYERa device is in Active Transmit Mode (ie the Transmit Mode bits (TMk20l) of the Current Transmit State Register (CTSR) are set to 00) and the PHY Invalid Bus is selected then the PLAYERa device will transmit a maximum of four Halt symbol pairs and then continuous Idle symbols due to the Repeat Filter when in the Repeat state D6 AIE A INDICATE ENABLE 0 Disables the A Indicate output port The A Indicate port pins will be tri-stated when the port is disabled 1 Enables the A Indicate output port (AIP AIC AIDk70l) D7 BIE B INDICATE ENABLE 0 Disables the B Indicate output port The B Indicate port pins will be tri-stated when the port is disabled 1 Enables the B Indicate output port (BIP BIC BIDk70l) Note Even though this bit can be set andor cleared in the DP83256 it will not affect any IOs since the DP83256 does not offer a B Indicate port 44 |
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