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DP83256 Datasheet(PDF) 70 Page - National Semiconductor (TI) |
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DP83256 Datasheet(HTML) 70 Page - National Semiconductor (TI) |
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70 / 144 page ![]() 50 Registers (Continued) 526 CURRENT INJECTION COUNT REGISTER (CIJCR) The Current Injection Count Register takes a snap-shot of the Injection Counter during every Control Bus Interface read cycle of this register During a Control Bus Interface write cycle the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) will be set to 1 and will ignore a write cycle The Injection Counter is an 8-bit down-counter which decrements every 80 ns The counter is active only during One Shot or Periodic Injection Modes (ie Injection Controlk10l bits (ICk10l)ofthe Current Transmit State Register (CTSR) are set to either 01 or 10) The Injection Threshold Register (IJTR) value is loaded into the Injection Counter when the counter reaches zero and during every Control Bus Interface write cycle of IJTR The counter is initialized to 0 during the reset process (ie ERSTeGND) ACCESS RULES ADDRESS READ WRITE 19h Always Write Reject D7 D6 D5 D4 D3 D2 D1 D0 IJC7 IJC6 IJC5 IJC4 IJC3 IJC2 IJC1 IJC0 Bit Symbol Description D0 – D7 IJC0 – IJC7 INJECTION COUNT BITk0-7l Current value of the Injection Counter IJC0 is the Least Significant Bit (LSB) 70 |
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