DP83256 datasheet(66/144 Pages) NSC

Part #	DP83256

Description	PLAYERa??Device (FDDI Physical Layer Controller)

PDF	144 Pages

Scroll/Zoom	100%

Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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66 / 144 page

50 Registers (Continued)

522 LINK ERROR THRESHOLD REGISTER (LETR)

The Link Error Threshold Register contains the start value for the Link Error Monitor Counter It is an 8-bit down-counter which

decrements if link errors are detected

When the Counter reaches 0 the Link Error Monitor Threshold Register value is loaded into the Link Error Monitor Counter and

the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition Register (ICR) is set to one

The Link Error Monitor Threshold Register value is also loaded into the Link Error Monitor Counter during every Control Bus

Interface write cycle of LETR

The counter is initialized to 0 during the reset process (ie ERSTeGND)

ACCESS RULES

ADDRESS

READ

WRITE

15h

Always

LET7

LET6

LET5

LET4

LET3

LET2

LET1

LET0

Bit

Symbol

Description

D0 – D7

LET0 – LET7

LINK ERROR THRESHOLD BIT k0–7l

Start value for the Link Error Monitor Counter

LET0 is the Least Significant Bit (LSB)

DP83256 Datasheet(PDF) 66 Page - National Semiconductor (TI)