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DP83256 Datasheet(PDF) 72 Page - National Semiconductor (TI) |
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DP83256 Datasheet(HTML) 72 Page - National Semiconductor (TI) |
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72 / 144 page  50 Registers (Continued) 528 CURRENT TRANSMIT STATE COMPARISON REGISTER (CTSCR) The Current Transmit State Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYERa device before it can be written to by the Control Bus Interface The current state of the Current Transmit State Register (CTSR) is automatically written into the Current Transmit State Comparison Register A (ie CTSCReCTSR) during a Control Bus Interface read cycle of CTSR During a Control Bus Interface write cycle the PLAYERa device will set the Conditional Write Inhibit bit (CWI) of the Interrupt Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within the CTSR when the value of a bit in the CTSR differs from the value of the corresponding bit in the Current Transmit State Comparison Register ACCESS RULES ADDRESS READ WRITE 1Bh Always Always D7 D6 D5 D4 D3 D2 D1 D0 RESC PRDPEC SEC IC1C IC0C TM2C TM1C TM0C Bit Symbol Description D0 TM0C TRANSMIT MODE k0l COMPARISON The comparison bit for the Transmit Mode k0l bit (TM0) of the Current Transmit State Register (CTSR) D1 TM1C TRANSMIT MODE k1l COMPARISON The comparison bit for the Transmit Mode k1l bit (TM1) of the Current Transmit State Register (CTSR) D2 TM2C TRANSMIT MODE k2l COMPARISON The comparison bit for the Transmit Mode k2l bit (TM2) of the Current Transmit State Register (CTSR) D3 IC0C INJECTION CONTROL k0l COMPARISON The comparison bit for the Injection Control k0l bit (IC0) of the Current Transmit State Register (CTSR) D4 IC1C INJECTION CONTROL k1l COMPARISON The comparison bit for the Injection Control k1l bit (IC1) of the Current Transmit State Register (CTSR) D5 SEC SMOOTHER ENABLE COMPARISON The comparison bit for the Smoother Enable bit (SE) of the Current Transmit State Register (CTSR) D6 PRDPEC PHY REQUEST DATA PARITY ENABLE COMPARISON The comparison bit for the PHY Request Data Parity Enable bit (PRDPE) of the Current Transmit State Register (CTSR) D7 RESC RESERVED COMPARISON The comparison bit for the Reserved bit (RES) of the Current Transmit State Register (CTSR) 72 |
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