DP83256 datasheet(89/144 Pages) NSC

89 / 144 page

60 Signal Descriptions

61 DP83256VF PIN DESCRIPTIONS

The pin descriptions for the DP83256VF are divided into 5 functional interfaces PMD Interface PHY Port Interface Control Bus

Interface Clock Interface and Miscellaneous Interface

For a Pinout Summary list refer to Table 8-1 and

Figure 8-1 DP83256VF 100-Pin JEDEC Metric PQFP Pinout

PMD INTERFACE

The PMD Interface consists of IO signals used to connect the PLAYERa device to the Physical Medium Dependant (PMD)

sublayer

Symbol

Description

PMIDa

PMD Indicate Data

Differential 100k ECL 125 Mbps serial data input signals from the PMD receiver

PMIDb

PMRDa

PMD Request Data

Differential 100k ECL 125 Mbps serial data output signals to the PMD transmitter

PMRDb

SDa

Signal Detect

Differential 100k ECL input signals from the PMD receiver indicating that a signal is being

received by the PMD receiver

SDb

TEL

PMD Transmitter Enable Level

A TTL input signal to select the PMD transmitter Enable (TXE) signal

level

TXE

PMD Transmitter Enable

A TTL output signal to enabledisable the PMD transmitter The output level

of the TXE pin is determined by three parameters the Transmit Enable (TE) bit in the Mode Register the

TM2-TM0 bits in the Current Transmit State Register and the input to the TEL pin The following rules

summarize the output of the TXE pin

1 If TEe0 and TELeGND then TXEeVCC

2 If TEe0 and TELeVCC then TXEeGND

3 If TEe1 and OTM and TELeGND then TXEeVCC

4 If TEe1 and OTM and TELeVCC then TXEeGND

5 If TEe1 and not OTM and TELeGND then TXEeGND

6 If TEe1 and not OTM and TELeVCC then TXEeVCC

DP83256 Datasheet(PDF) 89 Page - National Semiconductor (TI)