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DP83256 Datasheet(PDF) 85 Page - National Semiconductor (TI) |
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DP83256 Datasheet(HTML) 85 Page - National Semiconductor (TI) |
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85 / 144 page  50 Registers (Continued) 541 CLOCK GENERATION MODULE REGISTER (CGMREG) This register is used to enable or disable the 125 MHz ECL Transmit clock outputs These outputs are not required for use in a standard FDDI board implementation and are disabled by default to reduce high frequency noise These TXC outputs are included for support of alternate FDDI PMDs such as unshielded twisted pair copper cable DO NOT WRITE TO RESERVED REGISTER BITS Writes to reserved register bits could prevent proper device operation Therefore read the register first and then write it back with the non-reserved bits set to the desired value ACCESS RULES ADDRESS READ WRITE 3Bh Always Always D7 D6 D5 D4 D3 D2 D1 D0 RES RES FLTREN RES TXCE RES RES RES Bit Symbol Description D0-D2 RES RESERVED BITS DO NOT CHANGE THE VALUE OF THESE BITS Changes to reserved register bits could prevent proper device operation D3 TXCE TRANSMIT CLOCK ENABLE When bit is set to 1 125 MHz ECL TXC outputs are enabled When this bit is reset to 0 TXC outputs are disabled TXC outputs are disabled on reset Note TXC clocks are only available on the 160-pin DP83257 PLAYERa device D4 RES RESERVED BITS DO NOT CHANGE THE VALUE OF THESE BITS Changes to reserved register bits could prevent proper device operation D5 FLTREN FILTER ENABLE When bit is set to 1 the internal loop filter node is connected to the LPFLTR pin for diagnostic viewing This bit is reset to 0 by default which disconnects the filter node from the LPFLTR pin Note In normal operation this bit should be disabled (e0) D6-D7 RES RESERVED BITS DO NOT CHANGE THE VALUE OF THESE BITS Changes to reserved register bits could prevent proper device operation 85 |
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