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DP83256 Datasheet(PDF) 74 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83256
Description  PLAYERa??Device (FDDI Physical Layer Controller)
PDF  144 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83256 Datasheet(HTML) 74 Page - National Semiconductor (TI)

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50 Registers (Continued)
530 RECEIVE CONDITION COMPARISION REGISTER B (RCCRB)
The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYERa
device before it can be written to by the Control Bus Interface
The current state of RCRB is automatically written into the Receive Condition Comparison Register B (ie RCCRBeRCRB)
during a Control Bus Interface read cycle RCRB
During a Control Bus Interface write cycle the PLAYERa device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRB when the value of a bit in RCRB differs
from the value of the corresponding bit in the Receive Condition Comparison Register B
ACCESS RULES
ADDRESS
READ
WRITE
1Dh
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
RESC
SILSC
EBOUC
CSEC
LSUPVC
ALSC
STC
ILSC
Bit
Symbol
Description
D0
ILSC
IDLE LINE STATE COMPARISON
The comparison bit for the Idle Line State bit (ILS) of the Receive Condition
Register B (RCRB)
D1
STC
STATE THRESHOLD COMPARISON
The comparison bit for the State Threshold bit (ST) of the Receive
Condition Register B (RCRB)
D2
ALSC
ACTIVE LINE STATE COMPARISON
The comparison bit for the Active Line State bit (ALS) of the Receive
Condition Register B (RCRB)
D3
LSUPVC
LINE STATE UNKNOWN AND PHY VALID COMPARISON
The comparison bit for the Line State Unknown and
PHY Valid bit (LSUPV) of the Receive Condition Register B (RCRB)
D4
CSEC
CONNECTION SERVICE EVENT COMPARISON
CASCADE SYNCHRONIZATION ERROR
The comparison
bit for the Cascade Synchronization ErrorConnection Service Event bit (CSE) of the Receive Condition Register
B (RCRB)
D5
EBOUC
ELASTICITY BUFFER OVERFLOW
UNDERFLOW COMPARISON
The comparison bit for the Elasticity Buffer
OverflowUnderflow bit (EBOU) of the Receive Condition Register B (RCRB)
D6
SILSC
SUPER IDLE LINE STATE COMPARISON
The comparison bit for the Super Idle Line State bit (SILS) of the
Receive Condition Register B (RCRB)
D7
RESC
RESERVED COMPARISON
The comparison bit for the Reserved bit (RES) of the Receive Condition Register B
(RCRB)
74



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